1. Field of the Invention
The present invention relates to a test apparatus and a test method. More specifically, the invention relates to a test apparatus and a test method for testing a memory-under-test.
2. Related Art
FIG. 6 shows a configuration of a conventional test apparatus 600. The test apparatus 600 has a level comparator 604, a timing comparator 606 and a logical comparator 608.
The level comparator 604 compares voltage level of an output signal outputted from a device-under-test (hereinafter referred to as DUT) 602 and then the timing comparator 606 obtains it under strobe generated with timing decided in advance within the test apparatus 600.
Next, the logical comparator 608 compares the signal with an expected value to judge whether the DUT 602 is defect-free based on the comparison result.
It is noted that because the present applicant is unaware of existence of any prior art document at the present moment, description concerning to the prior art document will be omitted here.
Lately, there has been developed a high speed serial interface for communicating with a method of transmitting data by embedding clock therein from a transmitter side and of regenerating the clock from the data on a receiver side to receive the data with the regenerated clock.
The data of the high speed serial interface of such clock embedded method allows an uncertain width (jitter) of timing of predetermined scale. However, because timing of strobe for obtaining the output signal of the DUT 602 is decided in advance in the conventional test apparatus 600, it is unable to follow the fluctuation of timing of the output signal of the DUT 602. Therefore, there is a case when the device-under-test having the high speed serial interface as described above cannot be accurately tested.